Embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a three-dimensional (3-D) nonvolatile memory device and a method of manufacturing the same.
Technology for memory devices is developing toward a high degree of integration. In order to improve the degree of integration of memory devices, schemes for reducing the size of memory cells arranged in a 2-D way have been developed. As the size of the memory cells of the 2-D memory device is reduced, a multi-level cell (MLC) operation is not normally performed due to increased interference and disturbance. In order to overcome the limit of the 2-D memory device, a 3-D structured memory device for improving the degree of integration by arranging memory cells over a substrate in a 3-D way has been proposed. The 3-D structured memory device can improve the degree of integration, as compared with the case where memory cells are arranged in a 2-D way because the area of the substrate can be efficiently used.
The memory cells of the 3-D memory device include a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked and vertical channel layers configured to penetrate the conductive layers and the interlayer insulating layers. A variety of techniques are recently being proposed in order to improve reliability of the 3-D memory device.